Markets & Applications

 

Quantitative Finance

 

 

 

 

 

 

Overview & Challenges

The popular phrase “time is money,” rings no truer than in the financial world. The speed at which market analysis, risk management and data mining research need to take place are critical to this industry and to individual firms’ competitive advantage. 

 

In order to minimize risk, the compute algorithms are applying ever more sophisticated mathematics that are exponentially driving up the computation demands of financial houses. Computationally intensive financial applications such as these have historically run on large grids or clusters requiring high power, cooling and IT support costs.

 

Click here to download the SRC® industry brief on the quantitative financial market.

 

 

Other Markets:

o Defense/National Security

o Oil & Gas/Seismic Processing

o Unmanned Aerial Vehicles (UAVs)

o Medical Imaging

o Scientific & Academic Research

 

SRC® SOLUTIONS                                                                                                     
SRC MAPstation™ workstations and Scalable Systems & Servers can greatly accelerate transaction applications, data mining and data encryption for financial sector applications. SRC MAP processor-based computing solutions deliver large performance gains at greatly reduced power consumption over leading microprocessor-based systems.

 

Attributes of SRC scalable computing solutions that help achieve significant application performance gains include:

  • MAP processors, the SRC reconfigurable compute element, deliver orders of magnitude speedup over microprocessors, use very low power and generate very little heat
  • Real-time encryption of data as it streams through the system with near zero latency
  • Rotating Common Memory (RCM) that can store terabytes of historical market data and deliver the data to compute at a sustained rate of 3.6 GBytes/sec
  • GPIOX Cards that can have up to six parallel ethernet data paths in or out of the Series H MAP processors and provide packets of data to compute in less than 10 nanoseconds
  • Global Common Memories (GCM) that can read memory access patterns defined by an application and deliver the data to a MAP processor at 3.6 GBytes/sec. Example use:
       o The reuse of computed data defined for data structures in Gbytes of data in complicated Monte Carlo applications
  • Processor-to-processor communication bandwidths of 3.6 GBytes/sec

 

 
EASE OF PROGRAMMING WITH THE CARTE™ PROGRAMMING ENVIRONMENT  

The SRC Carte Programming Environment takes high-level language C or Fortran code, compiles portions of it to run on the implicitly controlled microprocessors and creates the configuration information needed for the explicitly controlled reconfigurable MAP® processors. Everything needed to control both types of processors is then combined by the Carte Programming Environment into a single Unified Executable. Carte software tools support code development and execution on the hardware, as well as in emulation and simulation environments.

 
Performance Gains                                                                                            

SRC Application Results

 

The following table illustrates the performance advantage of a single SRC Series H MAP® processor compared with a highly tuned code running on a standard microprocessor. The performance gains are achieved by the ability to implement a custom mix of functions for the subroutine.

 

Speedup numbers below include all overhead, including data movement. All data is for a single MAP processor or a single microprocessor core and assumed 100% scalability for the microprocessor cores. Comparisons of the MAP processor to actual microprocessor based systems would result in even higher speedups due to less than 100% scalability in multicore microprocessor systems.

 

APPLICATION MAP PERFORMANCE SPEEDUP: MAP PROCESSOR VS. STANDARD mP
Finance (Black Scholes) 300M/sec 90x*

* Speedup relative to a 3.0 GHz Xeon

 

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Related White Papers*                                                                                      
Black-Scholes Performance on the SRC-7
This paper describes the SRC® implementation of a Black-Scholes double precision floating point algorithm on several of its MAP® reconfigurable processors and the resulting speed-up compared to conventional microprocessor-based systems.

 

IMPLICIT+EXPLICIT™ Architecture
This paper explains the innovative SRC IMPLICIT+EXPLICIT Architecture, which fully integrates Dense Logic Device (DLD) technology and reconfigurable Direct Execution Logic (DEL) with the Carte Programming Environment, delivering orders of magnitude increases in performance.

 

* Please e-mail marketing@srccomputers with your contact information to obtain copies of the papers listed here

 

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Find Out More                                                                                                        
Contact SRC Computers today to find out how you can get more performance per watt over traditional microprocessor-based systems. 

Call (719) 262-0213 or e-mail sales@srccomputers.com to speak with our applications experts.

 

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