White Papers
The following SRC® and partner white papers are available upon request by emailing marketing@srccomputers.com. Please include your name and the name of your organization when requesting these documents.
SRC ATLAS™ Computer System
The ATLAS system from SRC Computers is a versatile compute system intended for use in harsh
environments including both ground based and airborne applications. ATLAS can incorporate a customer selected mix of
SRC APM processor modules, reconfigurable MAP® processors and Multi-Ported Common
Memory modules, interconnected with
the high bandwidth Hi-Bar® crossbar switch. The ATLAS system is a general purpose compute
solution that also offers extreme external I/O capability of up to 12 Gbytes/s per MAP processor, making
it ideal for use as a signal data processor.
SRC Computers' MAP Processors for Airborne Intelligence, Reconnaissance, and Surveillance Applications
This paper will present an overview of the SRC IMPLICIT+EXPLICIT™ Architecture, airborne system implementation, and Carte™ high-level language programming environment as well as the systems applicability to perform image and synthetic aperture radar processing. Specific airborne program examples of these two major application categories will also be presented.
SRC Computers' MAP Processors for Digital Image Processing
From unmanned vehicles to medical to remote sensing applications, the architecture of
the SRC MAP processor is well suited to high performance processing of large images from multiple sources. This paper presents several representative image processing algorithms implemented on the SRC-7 Series H MAP processor and compares their execution performance relative to a CPU.
Reverse Time Migration Performance on the SRC Series H MAP Processor
Reverse Time Migration is the most important seismic data processing method used to recover subsurface images of the Earth's interior.
This paper describes the evaluation of a compute intensive two-way finite-difference acoustic wave-propagation kernel used in the Reverse Time Migration technique and resulting significant performance gain over
traditional microprocessors.
Computed Tomography (CT) Scan Image Reconstruction on the SRC-7
The SRC-7 system architecture is well suited to accelerating of CT scan image reconstruction. In the simplest SRC-7 system implementation, a microprocessor is paired with a Series H MAP processor. These two processors working together achieve a 29x performance boost over the 3GHz 64-bit Xeon microprocessor working alone. This means that if a traditional computer takes 10 minutes to reconstruct a CT scan image, the SRC-7 system will take only 20 seconds to reconstruct the same image.
Black-Scholes Performance on the SRC-7
This paper describes SRC Computers' implementation of a Black-Scholes double precision floating point algorithm on several of its MAP reconfigurable processors and the resulting speed-up compared to conventional microprocessor-based systems.
Algorithm Optimization Case Study - SAR Backprojection
The Spotlight Synthetic Aperture Radar (SAR) Backprojection algorithm is considered to be the “gold standard” of the SAR imaging techniques. This paper describes a study that compared the performance of a MATLAB implementation of a 2D SAR Backprojection application to a MATLAB – MAP implementation and to an all C Language implementation.
Algorithm Optimization Case Study - Edge Detection
This paper will discuss the use of various standard program optimization techniques as applied to an edge detection application written in C for use on the SRC-7 Series H MAP processor. The SRC-7 Series H MAP
processor can yield more than two orders of magnitude performance improvements over a 3GHz Xeon microprocessor using Intel IPPLIB v5.1 image processing functions.
SRC MAPstation™ Image Processing: Two Dimensional Floating Point Fast Fourier Transforms
Using the complex floating point programmable FFT from SRC Computers’ image processing library, engineers have demonstrated a 2D FFT with a O(N) transpose operation. This means that every time image resolution grows by 2x, the image processing time grows by the same amount, thus allowing efficient and very high-resolution image processing in the frequency domain vs. traditional microprocessor methods. This O(N) transpose operation is achieved using the advanced memory architecture in
the SRC Series H MAP processor.
SRC MAPstation Image Processing: Intensity Histogram
Given the importance of the histogram operation, SRC recently developed a MAP histogram function specifically to support image applications. This paper will discuss this function as well as provide a detailed example of how to use the function in a MAP C program. Later papers will incorporate this simple function into real image applications and discuss realizable performance at the application level.
SRC Carte and Graphical User Interface (GUI) Programming
All capabilities available to the programmer under Linux remain
available in the Carte Programming Environment. Since Carte generates a single
integrated executable containing both CPU and MAP processor code,
it is often easiest to utilize the Carte Makefile for heterogeneous compilation.
This paper describes the development of a simple GTK based GUI application
program within the Carte Programming Environment, with emphasis on the Makefile.
Introduction to the SRC-7 MAPstation
This paper provides a general overview of the system architecture, components, software, and performance of the SRC-7 MAPstation class of systems.
First Level Application Screening
This paper describes system level requirements that SRC systems tend to be very well oriented toward; application areas where SRC systems have already achieved at least an order of magnitude performance improvement at the application level; and generalized software application features that are typically found in applications that benefit from the use of SRC technology.
Designing and Using FPGAs in Double-Precision Floating-Point Math (Altera Corporation)
This paper demonstrates the double-precision floating-point performance of Altera FPGAs through both theoretical “paper and pencil” calculations and real-world results.
Floating-Point Compiler -- Increasing Performance With Fewer Resources (Altera Corpoation)
Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. In addition, a new tool is introduced that will allow 100 percent of the floating-point capability of the FPGA device to be used.
IMPLICIT+EXPLICIT Architecture
This paper explains SRC Computers' innovative IMPLICIT+EXPLICIT architecture, which fully integrates Dense Logic Device (DLD) technology and reconfigurable Direct Execution Logic (DEL) with the Carte Programming Environment, delivering orders of magnitude increases in performance.
GPIOX Hardware Specifications
This paper defines all necessary parameters to allow third parties to successfully design GPIOX daughtercards for operation in conjunction with SRC MAP processors.
3D Pre-stack Wave Equation Depth Migration
The author of this paper, David Caliga, SRC Computers' Application Technology Manager, explains how the SRC reconfigurable MAP processor technology can accelerate processing time for compute-intensive floating point imaging such as the 3D Pre-stack Wave Equation Depth Migration (WEMIG).
Search Algorithm Performance
David Caliga, SRC Computers' Application Technology Manager, discusses how the SRC MAP processor technology can effect significant performance gains for applications such as database queries, internet searches, spam filters and bioinformatics computations.
Wavelet Versatility Benchmark
Dr. Wim Böhm and Dr. Jeff Hammes describe their research results in which they implement a wavelet image compression algorithm on the MAP-based SRC system and compare the performance of the SRC system to that of a microprocessor-based system.